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CS4351 192 kHz Stereo DAC with 2 Vrms Line Out
Features
Multi-bit Delta-Sigma Modulator 24-Bit Conversion Up to 192 kHz Sample Rates 112 dB Dynamic Range -100 dB THD+N +3.3 V, +9 to 12 V, and VL Power Supplies 2 Vrms Output into 5 k AC Load Digital Volume Control with Soft Ramp
- 119 dB Attenuation - 1/2 dB Step Size - Zero Crossing Click-Free Transitions
Description
The CS4351 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing, analog filtering, and on-chip 2 Vrms line level driver. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. These features are ideal for cost-sensitive, 2-channel audio systems including DVD players, A/V receivers, set-top boxes, digital TVs and VCRs, mini-component systems, and mixing consoles.
ATAPI Mixing Low Clock Jitter Sensitivity Popguard Technology(R) for Control of Clicks and Pops
ORDERING INFORMATION CS4351-CZ -10 to 70 C 20-pin TSSOP CS4351-CZZ, Lead Free -10 to 70 C 20-pin TSSOP CDB4351 Evaluation Board
I
1.8 V to 3.3V
3.3 V
9 V to 12 V
Hardware or I2 C/SPI Control Data Register/Hardware Configuration Reset Interpolation Filter with Volume Control Multibit Modulator
DAC
L e ve l T ra n s la to r
Amp + Filter
2 Vrms Line Level Left Channel Output
Serial Audio Input
PCM Serial Interface Interpolation Filter with Volume Control Multibit Modulator
DAC
Amp + Filter
2 Vrms Line Level Right Channel Output
Auto Speed Mode Detect Internal Voltage Reference
External Mute Control
Left and Right Mute Controls
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2004 (All Rights Reserved)
Sep `04 DS566PP2
CS4351
Table 1. Revision History Release A1 A2 A3 PP1 Date July 2003 August 2003 November 2003 June 2004 Changes Initial Release Added I2C/SPI switching characterics removed "Confidential", moved legal statement to last page Updated Legal. Updated Analog Performance specifications (Typ is improved). Consolidated speed mode performance for analog performance. Updated Current Consumption specifications (Typ and Min/Max increased). Updated PSRR (improved Typ performance for 60 Hz). Reduced recommended VBIAS+ capacitor in Typical Connection Diagram (to improve startup settling times). Changed bit 0 (POPG) in register 07h to reserved (must always be 1). Update w/ lead-free device ordering info.
PP2
Sep 2004
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TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................. 5 2. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 6 SPECIFIED OPERATING CONDITIONS ................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6 DAC ANALOG CHARACTERISTICS ....................................................................................... 7 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .......................... 9 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 10 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE .......................................... 11 SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT................................ 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 13 DIGITAL CHARACTERISTICS............................................................................................... 14 POWER AND THERMAL CHARACTERISTICS .................................................................... 14 3. TYPICAL CONNECTION DIAGRAM ..................................................................................... 15 4. APPLICATIONS ..................................................................................................................... 16 4.1 Sample Rate Range/Operational Mode Detect ............................................................... 16 4.1.1 Auto-Detect Enabled ........................................................................................... 16 4.1.2 Auto-Detect Disabled .......................................................................................... 16 4.2 System Clocking .............................................................................................................. 17 4.3 Digital Interface Format ................................................................................................... 18 4.3.1 Stand-Alone Mode .............................................................................................. 18 4.3.2 Control Port Mode .............................................................................................. 18 4.4 De-Emphasis Control ...................................................................................................... 19 4.4.1 Stand-Alone Mode .............................................................................................. 19 4.4.2 Control Port Mode ............................................................................................... 19 4.5 Recommended Power-up Sequence ............................................................................... 20 4.5.1 Stand-Alone Mode .............................................................................................. 20 4.5.2 Control Port Mode ............................................................................................... 20 4.6 Popguard(R) Transient Control .......................................................................................... 21 4.6.1 Power-up ............................................................................................................. 21 4.6.2 Power-down ........................................................................................................ 21 4.6.3 Discharge Time ................................................................................................... 21 4.7 Mute Control .................................................................................................................... 21 4.8 Grounding and Power Supply Arrangements .................................................................. 22 4.8.1 Capacitor Placement ........................................................................................... 22 4.9 Control Port Interface ...................................................................................................... 23 4.9.1 MAP Auto Increment ........................................................................................... 23 4.9.2 I2C Mode ............................................................................................................. 23 4.9.2.1 I2C Write ............................................................................................. 23 4.9.2.2 I2C Read ............................................................................................. 23 4.9.3 SPI Mode ............................................................................................................ 24 4.9.3.1 SPI Write ............................................................................................. 24 4.10 Memory Address Pointer (MAP) ................................................................................ 26 5. REGISTER QUICK REFERENCE .......................................................................................... 26 6. REGISTER DESCRIPTION .................................................................................................... 27 7. PARAMETER DEFINITIONS .................................................................................................. 34 8. PACKAGE DIMENSIONS ..................................................................................................... 35 9. APPENDIX ............................................................................................................................ 36
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LIST OF FIGURES
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Serial Input Timing ....................................................................................................... 11 Control Port Timing - I2C Format ................................................................................. 12 Control Port Timing - SPI Format (Write) ..................................................................... 13 Typical Connection Diagram ........................................................................................ 15 Left Justified up to 24-Bit Data ..................................................................................... 18 I2S, up to 24-Bit Data ................................................................................................... 18 Right Justified Data ...................................................................................................... 18 De-Emphasis Curve ..................................................................................................... 19 Control Port Timing, I2C Mode ..................................................................................... 24 Control Port Timing, SPI mode .................................................................................... 25 De-Emphasis Curve ..................................................................................................... 28 ATAPI Block Diagram .................................................................................................. 29 Single Speed (fast) Stopband Rejection ...................................................................... 36 Single Speed (fast) Transition Band ............................................................................ 36 Single Speed (fast) Transition Band (detail) ................................................................ 36 Single Speed (fast) Passband Ripple .......................................................................... 36 Single Speed (slow) Stopband Rejection ..................................................................... 36 Single Speed (slow) Transition Band ........................................................................... 36 Single Speed (slow) Transition Band (detail) ............................................................... 37 Single Speed (slow) Passband Ripple ......................................................................... 37 Double Speed (fast) Stopband Rejection ..................................................................... 37 Double Speed (fast) Transition Band ........................................................................... 37 Double Speed (fast) Transition Band (detail) ............................................................... 37 Double Speed (fast) Passband Ripple ......................................................................... 37 Double Speed (slow) Stopband Rejection ................................................................... 38 Double Speed (slow) Transition Band .......................................................................... 38 Double Speed (slow) Transition Band (detail) .............................................................. 38 Double Speed (slow) Passband Ripple ........................................................................ 38 Quad Speed (fast) Stopband Rejection ....................................................................... 38 Quad Speed (fast) Transition Band .............................................................................. 38 Quad Speed (fast) Transition Band (detail) .................................................................. 39 Quad Speed (fast) Passband Ripple ............................................................................ 39 Quad Speed (slow) Stopband Rejection ...................................................................... 39 Quad Speed (slow) Transition Band ............................................................................ 39 Quad Speed (slow) Transition Band (detail) ................................................................ 39 Quad Speed (slow) Passband Ripple .......................................................................... 39
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LIST OF TABLES
Table 1. Revision History ...............................................................................................................2 Table 2. CS4351 Auto-Detect .......................................................................................................16 Table 3. CS4351 Mode Select ......................................................................................................16 Table 4. Single-Speed Mode Standard Frequencies ....................................................................17 Table 5. Double-Speed Mode Standard Frequencies...................................................................17 Table 6. Quad-Speed Mode Standard Frequencies .....................................................................17 Table 7. Digital Interface Format - Stand-Alone Mode..................................................................18 Table 8. Digital Interface Formats .................................................................................................27 Table 9. ATAPI Decode ................................................................................................................29 Table 10. Example Digital Volume Settings ..................................................................................31
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1. PIN DESCRIPTION
SDIN SCLK LRCK MCLK VD GND DIF1(SCL/CCLK) DIF0(SDA/CDIN) DEM(AD0/CS) RST
Pin Name
SDIN SCLK LRCK MCLK VD GND RST VA VBIAS VQ VA_H VL BMUTEC AMUTEC AOUTB AOUTA Control Port Definitions SCL/CCLK SDA/CDIN AD0/CS Stand-Alone Definitions DIF0 DIF1 DEM
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VL AMUTEC AOUTA VA_H GND AOUTB BMUTEC VQ VBIAS VA
# 1 2 3 4 5 6 16 10 11 12 13 17 20 14 19 15 18
Pin Description
Serial Audio Data Input (Input) - Input for two's complement serial audio data. Serial Clock (Input) - Serial clock for the serial audio interface. Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power supply for the digital section. Ground (Input) - Ground reference. Reset (Input) - Powers down device and resets all internal resisters to their default settings when enabled. Low Voltage Analog Power (Input) - Positive power supply for the analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. High Voltage Analog Power (Input) - Positive power supply for the analog section. Serial Audio Interface Power (Input) - Positive power for the serial audio interface Mute Control (Output) - Control signal for optional mute circuit. Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteristics table.
7 8 9
Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data (Input/Output) - Input/Output for I2C data. Input for SPI data. Address Bit 0 / Chip Select (Input) - Chip address bit in I2C Mode. Control Port enable in SPI mode.
8 7 9
Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock, and Serial Audio Data. De-emphasis (Input) - Selects the standard 15 s/50 s digital de-emphasis filter response for 44.1 kHz sample rates
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2. CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical specifications are derived from performance measurements at TA = 25 C, VA_H = 12 V, VA = 3.3 V, VD = 3.3 V.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.) Parameters High Voltage Analog power Low Voltage Analog power Digital power Interface power Specified Temperature Range DC Power Supply Symbol VA_H VA VD VL TA Min 8.55 3.13 3.13 1.7 -10 Typ 12 3.3 3.3 3.3 Max 12.6 3.47 3.47 3.47 70 Units V V V V C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.) Parameters High Voltage Analog power Low Voltage Analog power Digital power Interface power Input Current, Any Pin Except Supplies Digital Input Voltage Digital Interface Ambient Operating Temperature (power applied) Storage Temperature DC Power Supply Symbol VA_H VA VD VL Iin VIN-L TA Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65 Max 14 3.63 3.63 3.63 10 VL+ 0.4 125 150 Units V V V V mA V C C
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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DAC ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz) Parameter All Speed Modes Dynamic Range (Note 2) 24-bit 16-bit Total Harmonic Distortion + Noise 24-bit 16-bit unweighted A-Weighted unweighted A-Weighted (Note 2) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Symbol Fs = 48, 96, and 192 kHz 99 102 109 112 95 98 -100 -89 -49 -92 -75 -35 109 100 -90 -79 -39 dB dB dB dB dB dB dB dB dB dB dB dB Min Typ Max Unit
All Speed Modes Idle Channel Noise / Signal-to-noise ratio Interchannel Isolation (1 kHz)
Notes: 1. One-half LSB of triangular PDF dither is added to data.
ANALOG CHARACTERISTICS (Continued)
Parameters Analog Output - All Modes Full Scale Output Voltage Common Mode Voltage Max DC Current draw from an AOUT pin Max Current draw from VQ Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance Symbol Min 1.9 5 Typ 2.0 4 10 1 0.1 100 50 Max 2.1 100 Units Vrms Vdc A A dB ppm/C k pF
VQ IOUTmax IQmax
ZOUT RL CL
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The
filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Fast Roll-Off Parameter Min Typ Max Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz Passband (Note 3) to -0.01 dB corner 0 .454 to -3 dB corner 0 .499 Frequency Response 10 Hz to 20 kHz -0.01 +0.01 StopBand 0.547 StopBand Attenuation (Note 4) 102 Total Group Delay (Fs = Output Sample Rate) 9.4/Fs Intra-channel Phase Deviation 0.56/Fs Inter-channel Phase Deviation 0 De-emphasis Error (Note 5) Fs = 32 kHz 0.23 (Relative to 1 kHz) Fs = 44.1 kHz 0.14 Fs = 48 kHz 0.09 Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96 kHz Passband (Note 3) to -0.01 dB corner 0 .430 to -3 dB corner 0 .499 Frequency Response 10 Hz to 20 kHz -0.01 0.01 StopBand .583 StopBand Attenuation (Note 4) 80 Total Group Delay (Fs = Output Sample Rate) 4.6/Fs Intra-channel Phase Deviation 0.03/Fs Inter-channel Phase Deviation 0 Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192 kHz Passband (Note 3) to -0.01 dB corner 0 .105 to -3 dB corner 0 .490 Frequency Response 10 Hz to 20 kHz -0.01 0.01 StopBand .635 StopBand Attenuation (Note 4) 90 Total Group Delay (Fs = Output Sample Rate) 4.7/Fs Intra-channel Phase Deviation 0.01/Fs Inter-channel Phase Deviation 0 Unit Fs Fs dB Fs dB s s s dB dB dB Fs Fs dB Fs dB s s s Fs Fs dB Fs dB s s s
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (cont.)
Parameter Single Speed Mode - 48 kHz Passband (Note 3) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Output Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation De-emphasis Error (Note 5) (Relative to 1 kHz) Double Speed Mode - 96 kHz Passband (Note 3) Slow Roll-Off (Note 2) Min Typ Max to -0.01 dB corner to -3 dB corner 0 0 -0.01 .583 64 0 0 -0.01 .792 70 0 0 -0.01 .868 75 6.5/Fs 3.9/Fs 4.2/Fs 0.417 0.499 +0.01 0.14/Fs 0 0.23 0.14 0.09 .296 .499 0.01 0.01/Fs 0 .104 .481 0.01 0.01/Fs 0 Unit Fs Fs dB Fs dB s s s dB dB dB Fs Fs dB Fs dB s s s Fs Fs dB Fs dB s s s
(Note 4)
Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner to -3 dB corner
Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Total Group Delay (Fs = Output Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation Quad Speed Mode - 192 kHz Passband (Note 3) to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay Intra-channel Phase Deviation Inter-channel Phase Deviation
Notes: 2. Slow Roll-off interpolation filter is only available in Control Port mode. 3. Response is clock dependent and will scale with Fs. 4. For Single Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 5. De-emphasis is available only in Single Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone Mode. 6. Amplitude vs. Frequency plots of this data are available in "Appendix" on page 37.
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SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate (Manual selection) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs Fs Fs Fs tsclkl tsclkh Single Speed Mode Double Speed Mode Quad Speed Mode SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tsclkw tsclkw tsclkw tslrd tslrs tsdlrs tsdh Symbol Min 1.024 45 4 50 100 4 84 170 40 20 20
1 --------------------( 128 )Fs 1 -----------------( 64 )Fs 2 ---------------MCLK
Max 51.2 55 50 100 200 50 100 200 60 -
Units MHz % kHz kHz kHz kHz kHz kHz % ns ns ns ns ns ns
Input Sample Rate (Auto selection)
LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period
20 20 20 20
LR C K t slrd t slrs t sclkl t sclkh
S C LK t sdlrs S D ATA t sd h
Figure 1. Serial Input Timing
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CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, CL = 20 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 7) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns s s s s s s ns s ns s ns
Notes: 7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t S to p irs S t a rt R e p e a te d S t a rt t rd t fd S to p
SDA t buf t h d st t h igh t h d st t fc t su sp
SCL t t t sud t a ck t sust t rc
lo w
hdd
Figure 2. Control Port Timing - I2C Format
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, CL = 20 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 9) (Note 10) (Note 10) (Note 8) Symbol fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 Min 500 500 1.0 20 66 66 40 15 Max 6 100 100 Unit MHz ns ns s ns ns ns ns ns ns ns
Notes: 8. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 9. Data must be held for sufficient time to bridge the transition time of CCLK. 10. For FSCK < 1 MHz.
RST
t srs
CS t spi t css CCLK t r2
C D IN
t scl
t sch
t csh
t f2
t dsu t dh
Figure 3. Control Port Timing - SPI Format (Write)
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CS4351
DIGITAL CHARACTERISTICS
Parameters High-Level Input Voltage VL = 3.3 V VL = 2.5 V VL = 1.8 V VL = 3.3 V VL = 2.5 V VL = 1.8 V Symbol VIH VIH VIH VIL VIL VIL Iin Min 2.0 1.7 0.65*VL Typ 8 2 VA_H 0 Max 0.8 0.7 0.35*VL 10 Units V V V V V V A pF mA V V
Low-Level Input Voltage
Input Leakage Current Input Capacitance Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage
VOH VOL
POWER AND THERMAL CHARACTERISTICS
Parameters Power Supplies Power Supply Current (Note 11) normal operation, VA_H = 12 V VA_H = 9 V VA= 3.3 V VD= 3.3 V Interface current (Note 12) VL= 3.3 V power-down state, all supplies (Note 13) Symbol IA_H IA_H IA ID IL Ipd Min Typ 15 14 6 21 100 200 270 1 216 1 60 60 Max 20 19 8 26 400 354 285 Units mA mA mA mA A A mW mW mW mW dB dB
(Note 11) normal operation power-down (Note 13) VA_H = 9 V normal operation power-down (Note 13) Power Supply Rejection Ratio (Note 14) (1 kHz) (60 Hz)
Power Dissipation (all supplies) VA_H = 12 V
PSRR
Notes: 11. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are based on highest FS and highest MCLK. Variance between speed modes is small. 12. IL measured with no external loading on pin 8 (SDA). 13. Power down mode is defined as RES pin = Low with all clock and data lines held static. 14. Valid with the recommended capacitor values on VQ and VBIAS as shown in the typical connection diagram in Section 3.
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3. TYPICAL CONNECTION DIAGRAM
5.1 +3.3 V *
*Remove this supply if optional resistor is present. The decoupling caps should remain.
+3.3 V 10 F + 0.1 F 5 VD
*Optional
0.1 F 11 VA VBIAS+ 12
+
10 F + 3.3 F
4 Digital Audio Source 3 2 1
MCLK LRCK SCLK SDIN VA_H 17 0.1 F + 10 F +9 V to +12 V
Optional Mute Circuit +1.8 V to VD 20 0.1 F AMUTEC VL 19 560 2.2 nF* 576 k 412 k AOUTA
CS4351
AOUTA
18 + 3.3 F
10 k
Optional Mute Circuit BMUTEC 10 C/ Mode Configuration 7 8 9 RST DIF1(SCL/CCLK) DIF0(SDA/CDIN) DEM(AD0/CS) VQ GND 6 GND 15 13 + 3.3 F
*Shown value is for fc=130kHz
14 560 10k 2.2 nF* 576 k 412 k AOUTA
AOUTB
15 + 3.3 F
Figure 4. Typical Connection Diagram
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4. APPLICATIONS 4.1 Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode will depend on whether the Auto-Detect Defeat bit is enabled/disabled.
4.1.1
Auto-Detect Enabled
The Auto-Detect feature is enabled by default. In this state, the CS4351 will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 2. Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (FS) 4 kHz - 50 kHz 84 kHz - 100 kHz 170 kHz - 200 kHz MODE Single Speed Mode Double Speed Mode Quad Speed Mode
Table 2. CS4351 Auto-Detect
4.1.2
Auto-Detect Disabled
The Auto-Detect feature can be defeated only by the format bits in the control port register 02h. In this state, the CS4351 will not auto-detect the correct mode based on the input sample rate (Fs). The operational mode must then be set manually according to one of the ranges illustrated in Table 3. Please refer to section 6.2.3 for implementation details. Sample rates outside the specified range for each mode are not supported. In stand-alone mode it is not possible to disable auto-detect of sample rates.
FM1 0 0 1 1 FM0 0 1 0 1 Input Sample Rate (FS) Auto speed mode detect 4 kHz - 50 kHz 50 kHz - 100 kHz 100 kHz - 200 kHz Table 3. CS4351 Mode Select MODE Auto Single Speed Mode Double Speed Mode Quad Speed Mode
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4.2 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6. Refer to section 4.3 for the required SCLK timing associated with the selected Digital Interface Format, and SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE, page 11 for the maximum allowed clock frequencies.
Sample Rate (kHz) 32 44.1 48 MCLK (MHz) 512x 768x 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640
256x 8.1920 11.2896 12.2880
384x 12.2880 16.9344 18.4320
1024x 32.7680 45.1584 49.1520
1152x 36.8640
Table 4. Single-Speed Mode Standard Frequencies
Sample Rate (kHz) 64 88.2 96 MCLK (MHz) 256x 16.3840 22.5792 24.5760
128x 8.1920 11.2896 12.2880
192x 12.2880 16.9344 18.4320
384x 24.5760 33.8688 36.8640
512x 32.7680 45.1584 49.1520
Table 5. Double-Speed Mode Standard Frequencies
Sample Rate (kHz) 176.4 192 MCLK (MHz) 128x 22.5792 24.5760
64x 11.2896 12.2880
96x 16.9344 18.4320
192x 33.8688 36.8640
256x 45.1584 49.1520
Table 6. Quad-Speed Mode Standard Frequencies
= Denotes clock modes which are NOT auto detected
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4.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated in Table 7, and 1 of 6 formats in Control Port mode, as illustrated in Table 8.
4.3.1
Stand-Alone Mode
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figures 5-7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2, and 48 cycles per LRCK period in format 3.
DIF0 0 0 1 1 DIF1 0 1 0 1
I2S, up to 24-bit Data Left Justified, up to 24-bit Data Right Justified, 24-bit Data Right Justified, 16-bit Data
DESCRIPTION
FORMAT 0 1 2 3
FIGURE 6 5 7 7
Table 7. Digital Interface Format - Stand-Alone Mode
4.3.2
Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section 6.2.1) . For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 5-7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and 36 cycles in format 5.
LR C K L e ft C h a n n e l R ig h t C h a n n e l
SCLK
S D IN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LS B
Figure 5. Left Justified up to 24-Bit Data
LR CK L e ft C h a n n e l R ig h t C h a n n e l
SCLK
S D IN
M SB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 6. I2S, up to 24-Bit Data
LR C K L e ft C h a n ne l R ig h t C h a n n e l
SC LK
SD IN
M SB
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LS B
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LS B
Figure 7. Right Justified Data
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4.4 De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 8 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 8. De-Emphasis Curve Notes: De-emphasis is only available in Single-Speed Mode.
4.4.1
Stand-Alone Mode
When pulled to VL the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND the DEM pin turns off the de-emphasis filter.
4.4.2
Control Port Mode
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section 6.2.2 for the desired de-emphasis control.
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4.5 Recommended Power-up Sequence 4.5.1 Stand-Alone Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default settings, VQ will remain low, and VBIAS will be connected to VA. 2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-Alone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.5.2
Control Port Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default settings, VQ will remain low, and VBIAS will be connected to VA. 2. Bring RST high. The device will remain in a low power state with VQ low. 3. Perform a control port write to the CP_EN bit prior to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1. 4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 s when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description of power-up timing.
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4.6 Popguard(R) Transient Control
The CS4351 uses a novel technique to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.
4.6.1
Power-up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing audible power-up transients.
4.6.2
Power-down
To prevent audible transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
4.6.3
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.7
Mute Control
The Mute Control pins go active during power-up initialization, reset, muting (see section 6.4.3), or if the MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Please see "Typical Connection Diagram" on page 15 for a suggested mute circuit for single supply systems. This FET circuit must be placed in series after the RC filter, otherwise noise may occur during muting conditions. Further ESD protection will need to be taken into consideration for the FET used. If dual supplies are available, the BJT mute circuit from Figure 12 in the CS4398 datasheet (active Low) may be used.
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4.8 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4351 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 4 shows the recommended power arrangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4351 should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted coupling into the DAC.
4.8.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin.
Notes: All decoupling capacitors should be referenced to analog ground.
The CDB4351 evaluation board demonstrates the optimum layout and power supply arrangements.
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4.9 Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I2C or SPI.
4.9.1
MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
4.9.2
I2C Mode
In the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 9 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (100110[AD0][R/W]) and should be tied to VL or GND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected.
4.9.2.1 I2C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 7. 1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4) If the INCR bit (see section 4.9.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I2C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.
4.9.2.2 I2C Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifications.
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1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2) After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP, or the default address (see section 4.10.2) if an I2C read is the first operation performed on the device. 3) Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. 4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I2C Write instructions followed by step 1 of the I2C Read section. If no further reads from other registers are desired, initiate a STOP condition to the bus.
N O TE SDA
1 00 1 10 AD 0 R /W ACK D AT A 1-8 ACK D A TA 1-8 ACK
SCL
S ta rt
S top
N O TE : If operation is a w rite, this byte contains the M em ory A ddress P ointer, M A P . If operation is a read, this byte contains the data of the register pointed to by the M A P .
Figure 9. Control Port Timing, I2C Mode
4.9.3
SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 10 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK.
4.9.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Section 7. 1) Bring CS low. 2) The address byte on the CDIN pin must then be 10011000. 3) Write to the memory address pointer, MAP. This byte points to the register to be written.
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4) Write the desired data to the register pointed to by the MAP. 5) If the INCR bit (see section 4.9.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high.
CS C C LK C H IP ADDRESS C DIN
1001100
R /W
MAP
MSB
D A TA
LSB
byte 1 M A P = M em ory A d dress P oin te r
byte n
Figure 10. Control Port Timing, SPI mode
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4.10 Memory Address Pointer (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
4.10.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = `0' 0 - Disabled 1 - Enabled
4.10.2 MAP (MEMORY ADDRESS POINTER)
Default = `0000'
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5.
1h 2h 3h
REGISTER QUICK REFERENCE
Function
Chip ID default Mode Control default Volume, Mixing, and Inversion Control default Mute Control default
Addr
7
PART4 1 Reserved 0 VOLB=A
6
PART3 1 DIF2 0 INVERTA
5
PART2
4
PART1 1 DIF0 0 Reserved
3
PART0 1 DEM1 0 ATAPI3
2
REV2 DEM0 0 ATAPI2
1
REV1 FM1 0 ATAPI1
0
REV0 FM0 0 ATAPI0
1
DIF1
0
INVERTB
0 AMUTE 1 VOL7 0 VOL7 0 SZC1 1 PDN 1
0 Reserved 0 VOL6 0 VOL6 0 SZC0 0 CPEN 0
0 MUTEC A=B 0 VOL5 0 VOL5 0 RMP_UP 1 FREEZE 0
0 MUTE_A 0 VOL4 0 VOL4 0 RMP_DN 1 Reserved 0
1 MUTE_B 0 VOL3 0 VOL3 0 Reserved 0 Reserved 0
0 Reserved 0 VOL2 0 VOL2 0 FILT_SEL 0 Reserved 0
0 Reserved 0 VOL1 0 VOL1 0 Reserved 0 Reserved 0
1 Reserved 0 VOL0 0 VOL0 0 Reserved 1 Reserved 0
4h
5h
Channel A Volume Control default Channel B Volume Control default Ramp and Filter Control default Misc. Control default
6h
7h
8h
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6.
6.1
REGISTER DESCRIPTION
Chip ID - Register 01h
7 PART4 1 6 PART3 1 5 PART2 4 PART1 1 3 PART0 1 2 REV2 1 REV1 0 REV0 -
** All register access is R/W unless specified otherwise**
1
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11111b and the remaining Bits (2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
6.2
Mode Control 1 - Register 02h
6 DIF2 0 5 DIF1 4 DIF0 0 3 DEM1 0 2 DEM0 0 1 FM1 0 0 FM0 0
7 Reserved 0
0
6.2.1
DIGITAL INTERFACE FORMAT (DIF2:0) BITS 6-4
Function: These bits select the interface format for the serial audio input. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 5-7. DIF2
0 0 0 0 1 1 1 1
DIF1
0 0 1 1 0 0 1 1
DIF0
0 1 0 1 0 1 0 1
DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data Reserved Reserved Table 8. Digital Interface Formats
Format
0 (Default) 1 2 3 4 5
FIGURE
5 6 7 7 7 7
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6.2.2 DE-EMPHASIS CONTROL (DEM1:0) BITS 3-2.
Default = 0 00 - No De-emphasis 01 - 44.1 kHz De-emphasis 10 - 48 kHz De-emphasis 11 - 32 kHz De-emphasis Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 11)
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 11. De-Emphasis Curve
Note: De-emphasis is only available in Single Speed Mode
6.2.3
FUNCTIONAL MODE (FM) BITS 1-0
Default = 00 00 - Auto speed mode detect 01 - Single-Speed Mode (4 to 50 kHz sample rates) 10 - Double-Speed Mode (50 to 100 kHz sample rates) 11 - Quad-Speed Mode (100 to 200 kHz sample rates) Function: Selects the required range of input sample rates or DSD Mode.
6.3
Volume Mixing and Inversion Control - Register 03h
B6 INVERT A 0 B5 INVERT B 0 B4 Reserved 0 B3 ATAPI3 1 B2 ATAPI2 0 B1 ATAPI1 0 B0 ATAPI0 1
B7 VOLB=A 0
6.3.1
CHANNEL A VOLUME = CHANNEL B VOLUME (VOLB=A) BIT 7
Function: When set to 0 (default) the AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes. When set to 1 the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and Volume Control Bytes, and the B Channel Bytes are ignored.
6.3.2
INVERT SIGNAL POLARITY (INVERT_A) BIT 6
Function: When set to 1, this bit inverts the signal polarity of channel A. When set to 0 (default), this function is disabled.
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6.3.3 INVERT SIGNAL POLARITY (INVERT_B) BIT 5
Function: When set to 1, this bit inverts the signal polarity of channel B. When set to 0 (default), this function is disabled.
6.3.4
ATAPI CHANNEL MIXING AND MUTING (ATAPI3:0) BITS 3-0
Default = 1001 - AOUTA=aL, AOUTB=bR (Stereo) Function: The CS4351 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 9 and Figure 12 for additional information.
Left Channel Audio Data A Channel Volume Control MUTE AoutA
Right Channel Audio Data
B Channel Volume Control
MUTE
AoutB
Figure 12. ATAPI Block Diagram
ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2]
AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2]
Table 9. ATAPI Decode
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6.4 Mute Control - Register 04h
6 Reserved 0 5 MUTEC A=B 0 4 MUTE_A 0 3 MUTE_B 0 2 Reserved 0 1 Reserved 0 0 Reserved 0
7 AMUTE 1
6.4.1
AUTO-MUTE (AMUTE) BIT 7
Function: When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. When set to 0 this function is disabled
6.4.2
AMUTEC = BMUTEC (MUTEC A=B) BIT 5
Function: When set to 0 (default) the AMUTEC and BMUTEC pins operate independently. When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
6.4.3
A CHANNEL MUTE (MUTE_A) BIT 4 B CHANNEL MUTE (MUTE_B) BIT 3
Function: When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any ramping due to the soft and zero cross function. When set to 0 (default) this function is disabled.
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6.5 Channel A Volume Control - Register 05h Channel B Volume Control - Register 06h
7 VOL7 0 6 VOL6 0 5 VOL5 0 4 VOL4 0 3 VOL3 0 2 VOL2 0 1 VOL1 0 0 VOL0 0
6.5.1
DIGITAL VOLUME CONTROL (VOL7:0) BITS 7-0
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments from 0 to -127.5 dB. Volume settings are decoded as shown in Table 10. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. The actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12.
Binary Code 00000000 00000001 00000110 11111111 Decimal Value 0 1 6 255 Volume Setting 0 dB -0.5 dB -3.0 dB -127.5 dB
Table 10. Example Digital Volume Settings
6.6
Ramp and Filter Control - Register 07h
7 SZC1 1 6 SZC0 0 5 RMP_UP 1 4 RMP_DN 1 3 Reserved 0 2 FILT_SEL 0 1 Reserved 0 0 Reserved 1
6.6.1
SOFT RAMP AND ZERO CROSS CONTROL (SZC1:0) BITS 7-6
Default = 10 SZC1 SZC0 0 0 1 1 Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal 0 1 0 1 Description Immediate Change Zero Cross Soft Ramp Soft Ramp on Zero Crossings
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does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp PCM Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp and Zero Cross Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
6.6.2
SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP) BIT 5
Function: When set to 1 (default), an un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change or error, and after changing the Functional Mode. This un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate un-mute is performed in these instances. Note: for best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
6.6.3
SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN) BIT 4
Function: When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate mute is performed prior to executing a filter mode change. Note: for best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
6.6.4
INTERPOLATION FILTER SELECT (FILT_SEL) BIT 2
Function: When set to 0 (default), the Interpolation Filter has a fast roll off. When set to 1, the Interpolation Filter has a slow roll off. The specifications for each filter can be found in the "Combined Interpolation & On-chip Analog Filter Response" on page 9, and response plots can be found in figures 15 to 36.
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6.7 Misc Control - Register 08h
7 PDN 1 6 CPEN 0 5 FREEZE 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0
6.7.1
POWER DOWN (PDN) BIT 7
Function: When set to 1 (default) the entire device will enter a low-power state and the contents of the control registers will be retained. The power-down bit defaults to `1' on power-up and must be disabled before normal operation in Control Port mode can occur. This bit is ignored if CPEN is not set.
6.7.2
CONTROL PORT ENABLE (CPEN) BIT 6 Function:
This bit is set to 0 by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode can be accessed by setting this bit to 1. This will allow operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode.
6.7.3
FREEZE CONTROLS (FREEZE) BIT 5
Function: When set to 1, this function allows modifications to be made to the registers without the changes taking effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. When set to 0 (default), register changes take effect immediately.
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7. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Intra-channel Phase Deviation The deviation from linear phase within a given channel. Inter-channel Phase Deviation The difference in phase between channels.
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8. PACKAGE DIMENSIONS
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1 SEATING PLANE A
E b2 SIDE VIEW
123
e
L
END VIEW
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0 NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4 MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8 MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4 MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.50 0.65 0.70 8
NOTE
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
Parameters Package Thermal Resistance
Symbol 20L TSSOP JA
Min -
Typ 72
Max -
Units C/Watt
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9. APPENDIX
0 0
-20
-20
Amplitude (dB)
Amplitude (dB)
-40
-40
-60
-60
-80
-80
-100
-100
-120 0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
-120 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 13. Single Speed (fast) Stopband Rejection
0
Figure 14. Single Speed (fast) Transition Band
0.02
-1
0.015
-2 0.01 -3 0.005
Amplitude (dB)
Amplitude (dB)
-4
-5
0
-6
-0.005
-7 -0.01 -8 -0.015
-9
-10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
-0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 15. Single Speed (fast) Transition Band (detail)
Figure 16. Single Speed (fast) Passband Ripple
0
0
-20
-20
Amplitude (dB)
-60
Amplitude (dB)
-40
-40
-60
-80
-80
-100
-100
-120 0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
-120 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 17. Single Speed (slow) Stopband Rejection
Figure 18. Single Speed (slow) Transition Band
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0
0.02
-1
0.015
-2 0.01 -3 0.005
Amplitude (dB)
Amplitude (dB)
-4
-5
0
-6
-0.005
-7 -0.01 -8 -0.015
-9
-10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
-0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 19. Single Speed (slow) Transition Band (detail)
Figure 20. Single Speed (slow) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 21. Double Speed (fast) Stopband Rejection
0
Figure 22. Double Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
Amplitude (dB)
5
Amplitude (dB)
4
0.005
0
6
0.005
7
0.01
8
9
0.015
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 23. Double Speed (fast) Transition Band (detail)
Figure 24. Double Speed (fast) Passband Ripple
38
DS566PP2
CS4351
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 25. Double Speed (slow) Stopband Rejection
0
Figure 26. Double Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15 0.2 Frequency(normalized to Fs)
0.25
0.3
0.35
Figure 27. Double Speed (slow) Transition Band (detail)
Figure 28. Double Speed (slow) Passband Ripple
0
0
20
20
40 Amplitude (dB)
Amplitude (dB)
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 29. Quad Speed (fast) Stopband Rejection
Figure 30. Quad Speed (fast) Transition Band
DS566PP2
39
CS4351
0
0.2
1
0.15
2
0.1
3
0.05
Amplitude (dB)
Amplitude (dB) 0.05 0.1 0.15 0.2
4
5
0
6
7
8
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1 0.15 Frequency(normalized to Fs)
0.2
0.25
Figure 31. Quad Speed (fast) Transition Band (detail)
Figure 32. Quad Speed (fast) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4 0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 33. Quad Speed (slow) Stopband Rejection
0
Figure 34. Quad Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.02
0.04 0.06 0.08 Frequency(normalized to Fs)
0.1
0.12
Figure 35. Quad Speed (slow) Transition Band (detail)
Figure 36. Quad Speed (slow) Passband Ripple
40
DS566PP2
CS4351
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
DS566PP2
41

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